In the fabrication of modern semiconductor devices, the ever increasing device density and decreasing device dimensions demand more stringent requirements in the packaging or interconnecting techniques in such high density devices. Conventionally, a flip-chip attachment method has been used in packaging of semiconductor chips. In the flip-chip attachment method, instead of attaching a semiconductor die to a lead frame in a package, an array of solder bumps is formed on the surface of the die. The formation of the solder bumps may be carried out in an evaporation method by using a composite material of tin and lead through a mask for producing a desired pattern of solder bumps. The technique of electrodeposition has been more recently developed to produce solder bumps in flip-chip packaging process.
Other techniques that are capable of solder-bumping a variety of substrates to form solder balls have also been proposed. The techniques generally work well in bumping semiconductor substrates that contain solder structures over a minimal size. For instance, one of such widely used techniques is a solder paste screening method which has been used to cover the entire area of an eight inch wafer. However, with recent trend in the miniaturization of device dimensions and the necessary reduction in bump-to-bump spacing (or pitch), the use of the solder paste screening technique has become more difficult.
Other techniques for forming solder bumps such as the controlled collapse chip connection (C4) technique and the thin film electrodeposition technique have also been used in recent years in the semiconductor fabrication industry. The C4 technique is generally limited by the resolution achievable by a molybdenum mask which is necessary for the process. Fine-pitched solder bumps are therefore difficult to be fabricated by the C4 technique. Similarly, the thin film electrodeposition technique which also requires a ball limiting metallurgy layer to be deposited and defined by an etching process which has the same limitations as the C4 technique.
In recent years, chip scale packages (CSP) have been developed as a new low cost packaging technique for high volume production of IC chips. One of such chip scale packaging techniques has been developed by the Tessera Company for making a so-called micro-BGA package. The micro-BGA package can be utilized in an environment where several of the packages are arranged in close proximity on a circuit board or a substrate much like the arrangement of individual tiles. Major benefits achieved by a micro-BGA package are the combined advantages of a flip chip assembly and a surface mount package. The chip scale packages can be formed in a physical size comparable to that of an IC chip even though, unlike a conventional IC chip such as a flip chip, the chip scale package does not require a special bonding process for forming solder balls. Furthermore, a chip scale package may provide larger number of input/output terminals than that possible from a conventional quad flat package, even though a typical quad flat package is better protected mechanically from the environment.
In a typical micro-BGA package, a flexible interposer layer (which may contain circuit) is used to interconnect bond pads on an IC chip to an array of solder bump connections located on a flexible circuit. The flexible circuit, normally of a thickness of approximately 25 nm, is formed of a polymeric material such as polyimide which is laminated to a silicon elastomer layer of approximately 150 nm thick. The silicon elastomeric layer provides flexibility and compliance in all three directions for relief of stresses and thermal expansion mismatches. To further reduce the fabrication cost of IC devices, it is desirable that if a whole wafer can be passivated to seal the IC dies on the wafer, and then be severed into individual IC dies from the wafer such that not only the benefits of a chip scale package can be realized, the packaging cost for the IC dies may further be reduced.
The conventional flip-chip bonding process requires multiple preparation steps for IC chips, i.e. the formation of aluminum bond pads on the chip, the under-bump-metallurgy process on the bond pads and the deposition of solder required in the bumping process. The substrate that the IC chip is bonded to requires a flux coating in order to ensure an acceptable bond strength is formed between the solder bumps and the conductive elements on the substrate surface. The flip chip bonding process further requires a reflow process for the bumps, a flux cleaning process to eliminate excess flux material from the surface of the bump, a drying process after the cleaning process, an underfill process for dispensing an underfill material, and an underfill curing process to minimize thermal stresses in the underfill and in the joint formed.
The conventional method for depositing solder bumps described above presents a number of processing difficulties. For instance, in modern high-density semiconductor devices, the distance between I/O pads in a peripheral array continuously being reduced. In order to maintain a minimal required distance between the I/O pads, an I/O pad redistribution process must be conducted such that the pads can be transformed from a peripheral array to an area array. During the pad redistribution process, a plurality of metal traces must be formed to extend the I/O pads from the periphery of an IC die to the center of the IC die. It is desirable that, in order to assure the reliability of the die, a stress buffer layer is provided under the plurality of metal traces to buffer, or absorb, the stress incurred during the fabrication processes and to avoid stress cracking or fracture of the metal traces. The application of the stress buffering layers has been difficult in that if too thin a layer is applied, the stress buffering effect is insufficient to ensure the reliability of the IC die. However, when too thicker a layer of the stress buffering material is applied, numerous processing difficulties are incurred in the application process. Even though commercial stress buffering materials have been available in the marketplace, the fabrication technology for applying such materials to a satisfactory thickness has not been developed.
In a co-pending application Ser. No. 09/761,487, assigned to the common assignee of the present invention, a wafer level package that incorporates dual stress buffer layers for I/O redistribution was disclosed. This is shown in FIGS. 1A and 1B. A silicon substrate 12 has a multiple number of IC chip 10 formed on top. Each of the IC chip 10 has at least one first I/O pad 14, at least one conductive plug 18 formed on top of the I/O pad 14 for conducting electricity, a first stress buffer layer 20 formed of an elastic material and covers a first dielectric layer 16 while exposing the top of the conductive plug 18. A second stress buffer layer 22, formed of an elastic material on top of the first stress buffer layer 20 in-between the conductive plugs 18. A plurality of conductive traces 24 each having a first end that is electrically connected to the conductive plug 18. A second end of the conductive traces 24 extend toward a center of the IC die 10. A second dielectric layer 26 is formed on top of the plurality of conductive traces 24 insulating the plurality of conductive traces from each other while exposing a plurality of second I/O pads 28. A plurality of solder balls 32 are formed on the plurality of second I/O pads 28 with a UBM (under bump metallurgy) layer 30 therein between. The plurality of solder balls 32 is arranged in an area array. The second stress buffer layer 22 may be formed of a single protruded island, as shown in FIG. 1B, on top of the first stress buffer layer 20, or formed of a plurality of protruded islands 22 on top of the first stress buffer layer 20, as shown in FIG. 1A.
The wafer level package structure 10 shown in FIGS. 1A and 1B, while capable of reducing the thermal stress caused by the different coefficient of thermal expansions of the different materials, nevertheless presents the problem that a sharp interface 35 is formed in-between the conductive plug 18 and the first stress buffer layer 20. Due to the different values of the coefficient of thermal expansion of the materials that form the conductive plug 18 and the first stress buffer layer 20, fracture is frequently discovered at the sharp joint, i.e. at the 90° joint, or interface 35 due to the coefficient of thermal expansion differences when the package is heated or cooled during processing.
It is therefore an object of the present invention to provide a wafer level package that incorporates dual compliant layers for I/O redistribution that does not have the drawbacks or shortcomings of the conventional wafer level packages.
It is another object of the present invention to provide a wafer level package that incorporates dual compliant layers for I/O redistribution that does not present any fabrication problems.
It is a further object of the present invention to provide a wafer level package that incorporates dual compliant layers for I/O redistribution wherein the layers are applied by a spin coating, a screen printing or a stencil printing technique.
It is another further object of the present invention to provide a wafer level package that incorporates dual compliant layers for I/O redistribution wherein a compliant material having a Young's modulus of less than 6 MPa is utilized.
It is still another object of the present invention to provide a wafer level package that incorporates dual compliant layers for I/O redistribution wherein two separate compliant layers are first formed prior to the formation of a plurality of metal traces on top.
It is yet another object of the present invention to provide a wafer level package that incorporates dual compliant layers for I/O redistribution wherein a first compliant layer and a second compliant layer are sequentially deposited onto an IC die each to a thickness between about 4 μm and about 100 μm.
It is still another further object of the present invention to provide a method for forming a wafer level package which can be carried out by depositing a first compliant layer and a second compliant layer sequentially by a technique selected from spin coating, screen printing, laminating, and stencil printing.
It is yet another further object of the present invention to provide a method for forming a wafer level package by incorporating dual compliant layers for I/O pad redistribution by forming a plurality of metal traces on top of two separate layers of compliant materials each having a Young's modulus of less than 6 MPa.